Filtering of PWM

Filtered PWM is a well-known technique to create an analogue signal using a single digitally controlled pin. This blog post shows which filter cutoff frequency is needed to get a desired DAC performance specified in ENOB.

The worst-case ripple scenario is 50% modulated PWM, as the fundamental frequency has highest amplitude. As the modulation deviates from 50% more energy is put into the higher harmonics while the fundamental frequency amplitude is reduced. This fact is used to simplify the design of the filter.

The peak amplitude of the fundamental frequency is given by $ a_1 = \frac{2V_o}{\pi} \sin (\pi D)$, where $D$ is the duty cycle (0 .. 1) and $V_o$ is the PWM amplitude. At 50% duty cycle, the peak amplitude of the fundamental will be 0.64 times the PWM voltage, which is equivalent to 1.27 times peak-peak. Note that this is actually higher than the PWM voltage! In effect, the fundamental is approximately 2.1 dB higher.

PWM filter design

Consider a desired ENOB of $b$ bits. This is equivalent to a ripple of less than $1.76 + 6 \cdot b$ dB with respect to the PWM voltage. Taking into account the fact that the fundamental is 2.1 dB higher than the PWM voltage in the worst case, the filter must attenuate the fundamental by at least $3.86 + 6 \cdot b$ dB.

As a first implementation, we will consider a first order RC filter. Such a filter has a roll off of 6 dB per octave, which is equivalent to 10 dB per decade. The cutoff frequency (in octaves $N$ below the PWM frequency) of the filter can now be estimated: $$N \approx \frac{3.86 + 6 \cdot b}{6}.$$ or equivalently: $$N \approx 0.64+ b.$$

Given the previous and the PWM frequency $F$ in Hertz, the actual cutoff frequency of the first order RC filter needs to be at least lower than: $$ F_{cut} = F \cdot 2^{-(0.64+b)}.$$

Design example #1

Most Arduino PWM pins have a carrier frequency of 490 Hz with a modulation resolution of 256 steps (8 bits). In order to get the performance of an 8-bit ENOB DAC, the cutoff frequency of the RC filter must be: $$ F_{cut} = 490 \cdot 2^{-8.64} = 1.2 \ \textrm{Hz} $$

Assume the resistor R of the RC filter is chosen to be 3k3 ohms, then: $$ C = \frac{1}{2 \pi \cdot R \cdot F_{cut}}.$$ Which gives $C \approx 40 \ \mu\textrm{F}$.

The time constant of this filter is $\tau = 0.132$ seconds. Thus, this is a rather slow filter.

Concatenating RC stages

The settling time of the filter can be increased by concatenating two first order stages. This increases the roll off from 6 to 12 dB per octave. Therefore, the number of octaves decreases and becomes: $$ N_{2} \approx \frac{3.86 + 6 \cdot b}{12} $$ or equivalently: $$ N_{2} \approx 0.32 + 0.5 \cdot b.$$

Design example #2

Taking the parameters for previous design example but with two RC stages, we get: $$ N_{2} \approx 4.32.$$

With R = 3k3, we get $C \approx 830 \ \textrm{nF}$. The time constant of each stage of the filter is $\tau = 2.739$ milliseconds. This is much faster than a single stage filter.

Care must be taken to ensure the second stage does not significantly load the first stage. This is accomplished by makeing the resistor of the second stage ten times larger and the capacitor ten times smaller.

Design tables

The following table relates the desired ENOB to a factor for a single or double stage PWM filter. The cutoff of the RC stage is determined by mulitplying the factor with the PWM frequency.

ENOB	Single	Double
4	0.0401	0.2
5	0.0201	0.142
6	0.01	0.1
7	0.00501	0.0708
8	0.00251	0.0501
9	0.00125	0.0354
10	0.000627	0.025
11	0.000313	0.0177
12	0.000157	0.0125
13	7.83e-05	0.00885
14	3.92e-05	0.00626

For example, if we wish to design a 12-bit ENOB PWM DAC with a PWM frequency of 490 Hz, the cutoff frequency of a single stage filter would need to be below 0.000157 * 490 = 0.077 Hz. This would be a rather slow DAC. Luckily there are ways to increase the PWM frequency of most Arduino systems.